16c95x Serial Port Driver Repack

Here’s a concise review of the 16c95x serial port driver, based on common implementations (e.g., in Linux kernel, embedded systems, or legacy OS environments).

Weaknesses

Non-standard extensions – Vendor-specific registers (e.g., for custom baud rates, GPIO) require custom patches if not in mainline.
FIFO size detection – Some kernel versions misdetect 128-byte FIFO as 64-byte; verify with setserial or tty_ioctl.
Power management – Sleep/wake transitions may lose FIFO data if driver doesn’t properly save/restore extended registers.
Documentation – Public driver code lacks detailed comments for 16C95x-specific trigger levels; you may need the datasheet.
Legacy OS – Windows or bare-metal drivers often only support 16550A defaults, wasting FIFO capacity.

Extended Registers (Via LCR = 0xBF)

Writing 0xBF to LCR (Line Control Register) accesses the extended register set at offsets 0x00–0x0F. Key extended registers for the driver: 16c95x serial port driver

| Offset | Register | Purpose | |--------|----------|---------| | 0x00 | EFR | Enhanced Function Register – enables auto flow control and special features | | 0x01 | XON1 | XON character 1 | | 0x02 | XON2 | XON character 2 | | 0x03 | XOFF1 | XOFF character 1 | | 0x04 | XOFF2 | XOFF character 2 | | 0x05 | TCR | Transmission Control Register – Rx trigger level for auto-RTS | | 0x06 | TLR | Trigger Level Register – Rx FIFO interrupt trigger | | 0x07 | TXLVL | Tx FIFO level (read) / Resume Tx (write) | | 0x08 | RXLVL | Rx FIFO level (read) | | 0x09 | IODIR | I/O pin direction (GPIO mode) | | 0x0A | IOSTATE | I/O pin state | | 0x0B | IOINTENA | I/O interrupt enable | | 0x0C | IOCONTROL | I/O control (e.g., RS-485 enable) | | 0x0D | EFCR | Extra Features Control – selects enhanced modes | Here’s a concise review of the 16c95x serial

The driver must manage bank switching carefully, restoring LCR after accessing extended registers. Weaknesses

2. Auto Hardware Flow Control (RTS/CTS)

The driver writes to the Enhanced Feature Register (EFR) and MCR bits 5-6. Unlike the 16550, the 16C95x can automatically deassert RTS when the FIFO reaches a threshold. The driver must set:

EFR bit 6 (auto CTS) and bit 7 (auto RTS).
MCR bits 5 and 6 for flow control enable.